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datasheet eight output differentia l buffer for pcie gen3 9db833 idt? eight output differential buffer for pcie gen3 1 9db833 rev c 052411 general description the 9db833 zero-delay buffer supports pcie gen3 requirements, while being backwards compatible to pcie gen2 and gen1. the 9db833 is driven by a differential src output pair from an idt 932s421 or 932sq420 or equivalent main clock generator. recommended application 8 output pcie gen3 zero-delay/fanout buffer output features ? 8 - 0.7v current-mode differential hcsl output pairs ? supports zero delay buffer mode and fanout mode ? selectable bandwidth ? 50-110 mhz operation in pll mode ? 5-166 mhz operation in bypass mode features/benefits ? 3 selectable smbus addresses; mulitple devices can share the same smbus segment ? oe# pins; suitable for express card applications ? pll or bypass mode; pll can dejitter incoming clock ? selectable pll bandwidth; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi ? smbus interface; unused outputs can be disabled ? supports undriven differential outputs in power down mode for power management key specifications ? outputs cycle-cycle jitter <50ps ? output to output skew <50ps ? phase jitter: pcie gen3 <1.0ps rm block diagram lock stop logic src_in src_in# dif(7:0)) control logic byp#_lobw_hibw smbdat smbclk pd# spread compatible pll 8 iref oe(7:0)# 8 m u x
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 2 9db833 rev c 052411 pin configuration operating mode readback table power connections tri-level input logic levels smbus address selection and readback src _div# 1 48 vdda vdd r 2 47 gnda gn d 3 46 ir ef src_i n 4 45 l ock src_in# 5 44 oe7# oe0# 643 oe4# oe3# 742dif_7 dif_0 8 41 dif_7# dif_0# 940 pd# gn d 10 39 v dd vd d 11 38 di f_ 6 dif_1 12 37 dif_6# dif_1# 13 36 oe6# oe1# 14 35 oe5# oe2# 15 34 di f_5 dif_2 16 33 dif_5# dif_2# 17 32 gnd gn d 18 31 v dd vd d 19 30 di f_ 4 dif_3 20 29 dif_4# dif_3# 21 28 smb_adr_tri byp#_hibw_lobw 22 27 vdd smbclk 23 26 gnd sm bdat 24 25 gnd notes: 9db833 highlighted pins are the differences between 9db803 and 9db833. pin 22 and pin 28 are latched on power up. please make sure that the power supply to the pullup/pulldown resist ors ramps at the same time as the main supply to the chip. byp#_lobw_hib w mode byte0, bit 3 byte 0 bit 1 low bypass 0 0 mid pll 100m h i bw 1 0 high pll 100m low bw 0 1 vdd gnd 23 src_in/src_in# 6,11,19,31,39 10,18, 25,32 dif(7:0) 27 26 digital vdd/gnd 48 47 analog vdd/gnd for pll in iref for best results, treat pin 2 as analog vdd. description pin number state of pin voltage low <0.8v m id 1 .2 2.0v smb_adr_tri address low da/db mid dc/dd high d8/d9
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 3 9db833 rev c 052411 pin descriptions pin # pi n name pin type descr iption 1src_div# in active low input for determining src output frequency src or src/2. 0 = src/2, 1= src 2vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analo g p ower rail and filtered a pp ro p riatel y . 3 gnd pwr ground pin. 4 src_in in 0.7 v d ifferential sr c true input 5 src_in# in 0.7 v differential src complementary input 6oe0# in active low input for enabling dif pair 0. 1 =disable outputs, 0 = enable outputs 7oe3# in active low input for enabling dif pair 3. 1 =disable outputs, 0 = enable outputs 8 dif_0 out 0.7v differential true clock output 9 dif_0# out 0.7v differential complementary clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_1 out 0.7v differential true clock output 13 dif_1# out 0.7v differential complementary clock output 14 oe1# in active low input for enabling dif pair 1. 1 =disable outputs, 0 = enable outputs 15 oe2# in active low input for enabling dif pair 2. 1 =disa ble out p uts, 0 = enable out p uts 16 dif_2 out 0.7v differential true clock out p ut 17 dif_2# out 0.7v differential com p le menta r y clock out p ut 18 gnd pwr ground p in . 19 vdd pwr power su pp l y , nominal 3.3v 20 dif_3 out 0.7v differential true clock out p ut 21 dif_3# out 0.7v differential com p le menta r y clock out p ut 22 byp#_hibw_lobw in tri-level in p ut to select b yp ass mode, hi bw pll, or lo bw pll mode 23 smbc lk in clock p in o f sm bus circu itr y , 5v tolerant 24 smbd at i/o dat a p in of smbus circuitr y , 5v tolerant
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 4 9db833 rev c 052411 pin descriptions (cont.) pin # pi n name pin type descr iption 25 gnd pwr ground pin. 26 gnd pwr ground pin. 27 vdd pwr power supply, nominal 3.3v 28 smb_ adr_ tri in smbus address select bit. this is a tri-level input that decodes 1 of 3 smbus addresses. 29 dif_4# out 0.7v differential complementary clock output 30 dif_4 out 0.7v differential true clock output 31 vdd pwr power supply, nominal 3.3v 32 gnd pwr ground pin. 33 dif_5# out 0.7v differential complementary clock output 34 dif_5 out 0.7v differential true clock output 35 oe5# in active low input for enabling dif pair 5. 1 =disable outputs, 0 = enable outputs 36 oe6# in active low input for enabling dif pair 6. 1 =disable outputs, 0 = enable outputs 37 dif_6# out 0.7v differential complementary clock output 38 dif_6 out 0.7v differential true clock output 39 vdd pwr power supply, nominal 3.3v 40 pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal osc. (if any) are stopped. 41 dif_7# out 0.7v differential com p lementar y clock out p ut 42 dif_7 out 0.7v differential true clock out p ut 43 oe4# in active low input for enabling dif pair 4 1 =disable out p uts, 0 = enable out p uts 44 oe7# in active low input for enabling dif pair 7. 1 =disable out p uts, 0 = enable out p uts 45 lock out 3.3v output indicating pll lock status. this pin goes high when lock is achieved. 46 iref out this pin establishes the reference for the differential current-mode output pairs. it requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. other impedances require different values. see data sheet. 47 gnda pwr ground pin for the pll core. 48 vdda pwr 3.3v power for the pll core.
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 5 9db833 rev c 052411 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9db833. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters electrical characterist ics?current consumption parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda/r 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 i nput low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsm b smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 2 o p eration under these conditions is neither im p lied nor g uaranteed. ta = t com or t i nd; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input h igh voltage - dif_in v ihd if differential inputs ( sin g le-ended measurement ) 600 800 1150 mv 1 input low voltage - d if_in v il dif differential inputs ( sin g le-ended measurement ) v ss - 300 0300mv1 i nput c ommon mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - d if_in v swing pea k t o pe ak va lue 30 0 1 450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty c ycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j dif in differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured throu g h +/-75mv window centered around differential zero ta = t com or t i nd; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = full load; 170 200 ma 1 i dd3 .3pd all diff pairs driven 53 60 ma 1 i d d3.3 pdz all different ial pairs tri-stated 3 6 ma 1 1 guaranteed by design and characterization, not 100% tested in production. pow erdown current
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 6 9db833 rev c 052411 electrical characteristics?input/ supply/common output parameters ta = t com or t i nd; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t com c ommmercial range 0 70 c 1 t ind industrial range -40 85 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level in p uts 2 v dd + 0.3 v1 i nput low voltage v il single-ended inputs, except smbus, low threshold and tri-level in p uts gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i in p sin gle -e nded inp uts v in = 0 v; inputs with internal pull-up resistors v in = vdd; input s w ith internal pull-down resistors -200 200 ua 1 f ibyp v dd = 3.3 v, bypass mode 5 166 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 50 100.00 110 mhz 2 pin i nductance l pin 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c in dif _in dif_in diff erential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 c lk sta bilization t stab from v dd pow er-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency f mod in allowable frequency (triang ular modu lation) 30 33 khz 1 oe# latency t latoe# d if st art after oe# assertion dif sto p af ter oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif outp ut en able afte r pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r r ise time of control inputs 5 ns 1,2 smbus input low voltage v il smb 0.8 v 1 smbus input high voltage v ihsm b 2.1 v dd smb v1 smbus output low voltage v ol s mb @ i pu llu p 0.4 v 1 smbus sink current i pul lup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operat ing frequen cy f max smb maximum smbus operating frequency 100 khz 1,5 1 guaranteed b y desi g n and characterization, not 100% tested in p roduct ion. 2 c ontrol input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for the smbus to be active ambient operating temperature input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance inpu t fre quen cy
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 7 9db833 rev c 052411 electrical characteristics?dif 0.7v current mode differential outputs electrical characteris tics?output duty cycle, jitter , skew and pll characterisitics t a = t com or t ind ; supply voltage vdd = 3.3 v +/-5% parameter sym bol conditions min typ max u nits notes slew rate trf scope averaging on 1 2 4 v/ns 1, 2, 3 slew rate matching trf slew rate matching, scope averaging on 20 % 1, 2, 4 voltage high vhigh 660 800 850 1 voltage low vlow -150 150 1 max voltage vmax 1150 1 min voltage vmin -300 1 vsw ing vswing scope averaging off 300 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 550 mv 1, 5 crossing voltage (var) -vcross scope averaging off 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. n ote that this is a subset of v_cross_min/max (v_cros s absolute) allowed. the intent is to limit vcross induced modulation by setting v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? (100 ? differential impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for c lock#. it is measured using a +/-75mv window centered on the average cross point where c lock rising meets clock# falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). ta = t com or t i nd; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 2. 7 4 mhz 1 -3db point in low bw mode 0.7 1. 1 1.4 mhz 1 pll jitter peaking t jpeak peak pass band gain 1. 5 2 db 1 duty cycle t dc measured differentially, pll mode 45 49 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mh z -2 2 % 1,4 t pdbyp bypass mode, v t = 50% 2500 4500/ 4900 ps 1,5 t pdpll pll mode v t = 50% -250 -50 250 ps 1 skew, output to output t sk 3 v t = 50% 50/60 ps 1,5 pll mode 50 ps 1,3 ad ditive jitter in bypass mode 50 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 3 measured from differential wavef orm 4 d uty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 5 first number is commercial temp, second number is industrial temp. skew, input to output jitt er, cycle to cycle t jcyc-cyc pll ban dwid th bw
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 8 9db833 rev c 052411 electrical characteristics?pc ie phase jitter parameters clock periods differential outp uts tracking spread spectrum clock periods differential outp uts not tracking spread spectrum ta = t com or t i nd; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ ma x units notes t jphpc ieg1 pcie gen 1 30 86 ps (p-p) 1,2,3 pcie ge n 2 l o ba nd 10khz < f < 1.5mhz 1. 0 3 ps ( rms ) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mh z) 2. 2 3.1 ps (rms) 1,2 t jphpc ieg3 pc ie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0. 5 1 ps (rms) 1,2,4 t jphpc ieg1 pcie gen 1 1 5 ps (p-p) 1,2,3 pcie ge n 2 l o ba nd 10khz < f < 1.5mhz 0. 1 0 .1 ps ( rms ) 1,2 pcie gen 2 high band 1.5mhz < f < n yq uist ( 50mh z ) 0. 2 0.3 ps ( rms ) 1,2 t jphpc ieg3 pc ie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0. 0 0.1 ps (rms) 1,2,4 1 applies to all ou tputs. 4 subject to final radification by pci sig. t jphpc ieg2 2 see http://www.pcisig.com for complete specs t jphpc ieg2 phase jitter, pll mode additive phase jitter, bypass mode 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum 9.949 9.999 10.024 10.025 10.026 10.051 10.101 ns 1,2,3 notes definition units measurement windo w symbol dif 100 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term average long-term average period long-term average short-term average period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100m 9.949 9.999 10.000 10.001 10.051 ns 1,2,3 1 guaranteed by desig n and characterization, not 100% tested in production. 3 driven by pcie output of main clock, pll mode or bypass mode 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck41 0b+ accuracy re quirements. the buffer itself does not contribute to ppm error. notes measurement windo w units symbol definition
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 9 9db833 rev c 052411 common r ecommendations for differential routing d imension or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max inch 1 l2 length, route as non-coupled 50ohm trace 0.2 max inch 1 l3 length, route as non-coupled 50ohm trace 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2 output termination and layout information hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: differential routing to pci express controller
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 10 9db833 rev c 052411 vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 termination for lvds and other common differential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts termination for cable ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 11 9db833 rev c 052411 general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address * ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit * assuming smb_adr_tri is at mid-level how to read ? controller (host) will send a start bit ? controller (host) sends the write address * ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address * ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit read address write address dd (h) dc (h) index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 12 9db833 rev c 052411 smb us table: frequency select register, r ead/write address (selectable) pin # name control function type 0 1 default bit 7 pd_mode pd# drive mode rw driven hi-z 1 bit 6 oe_mode oe#_stop drive mode rw driven hi-z 0 bit 5 0 bit 4 x bit 3 mode1 bypass#/pll1 rw input bit 2 1 bit 1 mode0 bypass#/pll0 rw input bit 0 src_div# src divide by 2 select rw x/2 x/1 1 smbus table: output control register pin # name control function t y pe 0 1 default bit 7 dif_7 output enable rw disable enable 1 bit 6 dif_6 output enable rw disable enable 1 bit 5 dif_5 output enable rw disable enable 1 bit 4 dif_4 output enable rw disable enable 1 bit 3 dif_3 output enable rw disable enable 1 bit 2 dif_2 out p ut enable rw disable enable 1 bit 1 dif_1 out p ut enable rw disable enable 1 bit 0 dif_0 output enable rw disable enable 1 note: the smbus output enable bit must be '1' and the respective oe pin must be active for the output to run! smbus table: oe pin control re g ister pin # name control function type 0 1 default bit 7 dif_7 dif_7 stoppable with oe7# rw free-run stoppable 0 bit 6 dif_6 dif_6 stoppable with oe6# rw free-run stoppable 0 bit 5 dif_5 dif_5 stoppable with oe5# rw free-run stoppable 0 bit 4 dif_4 dif_4 stoppable with oe4# rw free-run stoppable 0 bit 3 dif_3 dif_3 stoppable with oe3# rw free-run stoppable 0 bit 2 dif_2 dif_2 sto pp able with oe2# rw free-run sto pp able 0 bit 1 dif_1 dif_1 sto pp able with oe1# rw free-run sto pp able 0 bit 0 dif_0 dif_0 stoppable with oe0# rw free-run stoppable 0 smb us table: reserved re g ister pin # name control function type 0 1 default bit 7 x bit 6 x bit 5 x bit 4 x bit 3 x bit 2 x bit 1 x bit 0 x reserved reserved reserved reserved reserved reserved reserved reserved 16,17 12,13 8,9 byte 3 byte 2 42,41 38,37 34,33 - byte 1 30,29 20,21 34,33 30,29 20,21 16,17 12,13 8,9 42,41 38,37 byte 0 - - - - - - - reserved reserved reserved seeoperating mode readback table seeoperating mode readback table
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 13 9db833 rev c 052411 smbus table: vendor & revision id register pin # name control function t y pe 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vi d3 r - - 0 bit 2 vi d2 r - - 0 bit 1 vi d1 r - - 0 bit 0 vi d0 r - - 1 smb us table: device id pin # name control function type 0 1 default bit 7 rw 1 bit 6 rw 0 bit 5 rw 0 bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 1 bit 0 rw 1 smbus table: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 device id 1 device id 6 device id 7 (msb) device id is 83 hex for 9db833 device id 5 device id 4 device id 3 device id 0 device id 2 writing to this register configures how many bytes will be read back. - - - - - - - byte 6 - - vendor id - - - - - - byte 5 - byte 4 - - - - - revision id - - -
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 14 9db833 rev c 052411 pd#, power down the pd# pin cleanly shuts off all clocks and places the device into a power saving mode. pd# must be asserted before shutting off the input clock or power to insure an orderly shutdown. pd is asynchronous active-low input for both powering down the device and powering up the device . when pd# is asserted, all clocks will be driven high, or tri-stated (depending on the pd# drive mode and output control bits) before the pll is shut down. pd# assertion when pd# is sampled low by two consecutive rising edges of dif#, all dif outputs must be held high, or tri-stated (depending on the pd# drive mode and output control bits) on the next high-low transition of the dif# outputs. when the pd# drive mode bit is set to ?0?, all clock ou tputs will be held with dif driven high with 2 x i ref and dif# tri-stated. if the pd# drive mode bit is set to ?1?, both dif and dif# are tri-stated. pd# de-assertion power-up latency is less than 1 ms. this is the time from de-assertion of the pd# pin, or vdd reaching 3.3v, or the time from valid src_in clocks until the time that stable clocks are output from the device (pll locked). if the pd# drive mode bit is set to ?1?, all the dif outputs must driven to a voltage of >200 mv within 300 s of pd# de-assertion.
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 15 9db833 rev c 052411 package outline and package dimensions ( 48-pin tssop ) package dimensions are kept current with jedec publication no. 95 index area 1 2 48 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.0035 0.008 d 12.40 12.60 0.488 0.496 e 8.10 basic 0.319 basic e1 6.00 6.20 0.236 0.244 e 0.50 basic 0.020 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 16 9db833 rev c 052411 package outline and package dimensions (48-pin ssop) package dimensions are kept current with jedec publication no. 95 ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. index area 1 2 48 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.200.34.008.0135 c 0.130.25.005.010 d 15.75 16.00 .620 .630 e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e 0.635 basic 0.025 basic h 0.380.64.015.025 l 0.501.02.020.040 0 8 0 8 part / order number shipping packaging package temperature 9db833aflf tubes 48-pin ssop 0 to +70c 9db833aflft tape and reel 48-pin ssop 0 to +70c 9DB833AGLF tubes 48-pin tssop 0 to +70c 9DB833AGLFt tape and reel 48-pin tssop 0 to +70c 9db833afilf tubes 48-pin ssop -40 to +85c 9db833afilft tape and reel 48-pin ssop -40 to +85c 9db833agilf tubes 48-pin tssop -40 to +85c 9db833agilft tape and reel 48-pin tssop -40 to +85c
9db833 eight output differential buffer for pcie gen3 idt? eight output differential buffer for pcie gen3 17 9db833 rev c 052411 revision history r ev. issue d ate who description page # a 6/30/2010 rdw released to final b 5/9/2011 rd w 1. update pin 2 pin-name and pin description from vdd to vddr. this highlights that optimal peformance is obtained by treating vddr as in analog pin. this is a document update only, there is no silicon change. various c 5/24/2011 rdw 1. corrected pin description of pins 27/28 2. corrected orderable part number for 9db833agilft
? 2011 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9db833 eight output differential buf fer for pcie gen3 synthesizers

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